VHDL Model of a Half-Precision Floating-Point Arithmetic Unit with Remainder and Rounding

Abstract

Deep learning inference can be accelerated by using field-programmable gate arrays (FPGAs) and reduced-precision floating-point types, but existing half-precision arithmetic unit designs often do not fully comply with the IEEE 754-2008 standard, particularly in rounding and remainder operations. This paper describes a model of a synchronous, variable-latency, half-precision, floating-point arithmetic unit written in VHDL and synthesizable on an FPGA. The model, based on previous work, performs addition, multiplication, division, and remainder, and rounds the result using four of the five IEEE 754-2008 rounding modes. Its rounding algorithm is discussed in detail. The model was tested using 246 test vectors representing four operations, five floating-point data, five exceptions, and four rounding modes, simulated using Lattice Diamond 3.10 and Active-HDL 10.3. The model yielded correctly-rounded results to 244 of 246 test vectors. The two vectors that yielded inexact results involved a very large number multiplied by a very small number, attributable to insufficient intermediate storage width. Completion times with rounding ranged from 1 to 39 clock cycles for addition, 1 to 62 for multiplication, 1 to 102 for division, and 1 to 60 for remainder. The model has since been extended to single- and double-precision variants and verified on an FPGA, confirming its scalability across floating-point formats and its potential for use in deep learning inference applications.